Improvements in both speed and functionality of central processing units (CPUs) have generally resulted in accompanying improvements in memory devices to support the operation of these improved CPUs. One example of a memory device that has been designed to provide higher data processing speeds than conventional dynamic random access memories (DRAMs) is the Rambus DRAM (RDRAM). The Rambus DRAM typically includes a plurality of input receivers for converting the voltage level of an external data signal to a level suitable for circuitry internal to the Rambus DRAM. Each of the plurality of input receivers typically includes a differential amplifier for comparing the voltage level of the input data signal with a reference voltage. The differential amplifier generally includes a first NMOS transistor, which is gated by the input data signal, and a second NMOS transistor, which is gated by the reference voltage. When the input receivers operate simultaneously, an overlap capacitance may develop between the gate and the drain of the second NMOS transistor. As the overlap capacitance increases, the reference voltage may fluctuate to levels at which the plurality of input receivers may malfunction.
The fluctuation in the reference voltage may be characterized as noise impressed upon the reference voltage. In general, the noise level increases with distance from the source of the reference voltage. Thus, those input receivers positioned more distant from the location at which the reference voltage is applied may experience greater noise levels. An increase in the noise level may cause the input characteristics to differ between the various input receivers. Accordingly, different input receivers may yield different outputs for the same input data signal because of differences in the reference voltage level applied to the different input receivers caused by the noise.
In addition, the data set-up and hold times may also differ among the various input receivers. The input receivers typically operate in synchronization with a clock signal. The set-up time denotes the amount of time for which data must be input to an input receiver before the clock signal is transitioned while the hold time denotes the amount of time for which data must be continuously held after the clock signal is transitioned. Unfortunately, the input receivers may experience increasing margin loss in set-up time and hold time as their distance increases from the location at which the reference voltage is applied, which may cause the Rambus DRAM to malfunction.
Consequently, there exists a need for integrated circuit memory devices having improved immunity from reference voltage signal noise.